COPACOBANA V4-SX35, the Cost-Optimized Parallel COde Breaker, is an FPGA-based machine which is optimized for running cryptanalytic algorithms that can take advantage of a high amount of DSPs and the possibility to execute a multiply-add or accumulate function every clock at high frequencies. This machine consists of 128 FPGAs each with 192, 500MHz Xtreme-DSP-Cores giving you performace you never expect from a parallel computer.

Key features

• 128 Virtex-4 SX35 FPGAs per machine
• 24'576 XtremeDSP Slices at up to 500 MHz total
• 3456k bit block RAM per FPGA
• 1800W power usage; military-grade hardware possible
• Best DSP/$ ratio of all Virtex FPGAs

This reconfigurable parallel computer comes without external memory but provides a high throughput bus. Dataflow dominated and computation intensive target applications of naturally parallel problems fit perfectly to this architecture. DES and ECC cracking are such parallelizable problems: An exhaustive key search of the Data Encryption Standard (DES) takes  only a few days on average with COPACOBANA V4-SX35. Other ciphers can be attacked too, and COPACOBANA V4SX35 can also be used for parallel computing problems outside cryptanalysis like bioinformatics alignment (e.g. Smith-Waterman, Motif Search), Logistics Optimization (e.g. Simplex) and many others.